In a design flow, a concept for an integrated circuit design is transformed into its final form. Physical synthesis is a stage in the design flow of an integrated circuit where a gate-level netlist representing the integrated circuit design is utilized to optimize the physical characteristics of the integrated circuit design. These characteristics may include timing, power, testability, signal integrity, routability, and manufacturability. The physical characteristics of the integrated circuit design may be optimized subject to assigning the gates in the netlist to non-overlapping locations in the integrated circuit design.
Large-scale industrial static timing analysis (STA) engines are the backbone for modern physical synthesis flows. STA engines typically maintain fault-tolerant graph-based structures in order to provide a global interface for components to query current timing conditions (e.g., to extract the critical paths of a network) and update the values of edges between existing nodes in the graph (e.g., to reflect the re-powering or replacing of logical gates). STA engines are also responsible for propagating timing information throughout the entire network.